View LT1738EGTR_4108596.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 lt1738 1738fa the lt ? 1738 is a switching regulator controller designed to lower conducted and radiated electromagnetic interfer- ence (emi). ultralow noise and emi are achieved by controlling the voltage and current slew rates of an exter- nal n-channel mosfet switch. current and voltage slew rates can be independently set to optimize harmonic content of the switching waveforms vs efficiency. the lt1738 can reduce high frequency harmonic power by as much as 40db with only minor losses in efficiency. the lt1738 utilizes a current mode architecture opti- mized for single switch topologies such as boost, flyback and cuk. the ic includes gate drive and all necessary oscillator, control and protection circuitry. unique error amp circuitry can regulate both positive and negative voltages. the internal oscillator may be synchronized to an external clock for more accurate placement of switch- ing harmonics. protection features include gate drive lockout for low v in , soft-start, output current limit, short-circuit current limit- ing, gate drive overvoltage clamp and input supply undervoltage lockout. n greatly reduced conducted and radiated emi n low switching harmonic content n independent control of output switch voltage and current slew rates n greatly reduced need for external filters n single n-channel mosfet driver n 20khz to 250khz oscillator frequency n easily synchronized to external clock n regulates positive and negative voltages n easier layout than with conventional switchers n power supplies for noise sensitive communication equipment n emi compliant offline power supplies n precision instrumentation systems n isolated supplies for industrial automation n medical instruments n data acquisition systems , ltc and lt are registered trademarks of linear technology corporation. ultralow noise 5v to 12v converter 3 10 11 13 shdn cap nfb lt1738 gnd v in 17 14 2 gcl ss v5 sync gate 5 1 c t 6 r t 7 8 r csl 16 v c 15 12 r vsl cs 4 pgnd 20 fb 9 5pf si9426 10nf 1.5k 3.3k 25k 25k 3.3k 16.9k 1.3nf 22nf 0.22 f 21.5k 2.5k 10 h optional 150 f oscon 4 150 f oscon 12v 1a mbrd620 5v v in 100 f p3 22 h 1738 ta01 + + + a b 25m 12v output noise (bandwidth = 100mhz) 400 m v p-p 5 m s/div 1738 ta01a slew rate controlled ultralow noise dc/dc controller applicatio s u features typical applicatio u descriptio u point b on schematic 50mv/div point a on schematic 500 m v/div
2 lt1738 1738fa (note 1) supply voltage (v in ) ................................................ 20v gate drive current ..................................... internal limit v5 current ................................................. internal limit shdn pin voltage .................................................... 20v feedback pin voltage (trans. 10ms) ...................... 10v feedback pin current ............................................ 10ma negative feedback pin voltage (trans. 10ms) ........ 10v cs pin .......................................................................... 5v gcl pin ..................................................................... 16v ss pin .......................................................................... 3v operating junction temperature range (note 3) ............................................ C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number lt1738eg lt1738ig t jmax = 150 c, q ja = 110 c/ w electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 12v, v c = 0.9v, v fb = v ref , r vsl , r csl = 16.9k, r t = 16.9k and other pins open unless otherwise noted. 1 2 3 4 5 6 7 8 9 10 top view g package 20-lead plastic ssop 20 19 18 17 16 15 14 13 12 11 gate cap gcl cs v5 sync c t r t fb nfb pgnd nc nc v in r vsl r csl shdn ss v c gnd symbol parameter conditions min typ max units error amplifiers v ref reference voltage measured at feedback pin l 1.235 1.250 1.265 v i fb feedback input current v fb = v ref l 250 1000 na fb reg reference voltage line regulation 2.7v v in 20v l 0.012 0.03 %/v v nfr negative feedback reference voltage measured at negative feedback pin l C2.56 C 2.50 C2.45 v with feedback pin open i nfr negative feedback input current v nfb = v nfr C37 C25 m a nfb reg negative feedback reference voltage line regulation 2.7v v in 20v l 0.009 0.03 %/v g m error amplifier transconductance d i c = 50 m a 1100 1500 2200 m mho l 700 2500 m mho i esk error amp sink current v fb = v ref + 150mv, v c = 0.9v l 120 200 350 m a i esrc error amp source current v fb = v ref C 150mv, v c = 0.9v l 120 200 350 m a v clh error amp clamp voltage high clamp, v fb = 1v 1.27 v v cll error amp clamp voltage low clamp, v fb = 1.5v 0.12 v a v error amplifier voltage gain 180 250 v/v fb ov fb overvoltage shutdown outputs drivers disabled 1.47 v i ss soft-start charge current v ss = 1v 9.0 12 m a consult ltc marketing for parts specified with wider operating temperature ranges.
3 lt1738 1738fa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 12v, v c = 0.9v, v fb = v ref , r vsl , r csl = 16.9k, r t = 16.9k and other pins open unless otherwise noted. symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: supply current specification includes loads on each gate as in figure 1a. actual supply currents vary with operating frequency, operating voltages, v5 load, slew rates and type of external fet. note 3: the lt1738e is guaranteed to meet performance specifications from 0 c to 70 c. specifications from C40 c to 125 c are assured by oscillator and sync f max max switch frequency 250 khz f sync synchronization frequency range oscillator frequency = 250khz 290 khz v sync sync pin input threshold l 0.7 1.4 2 r sync sync pin input resistance 40 k w gate drive dc max maximum switch duty cycle r vsl = r csl = 3.9k, l 90 93.5 % osc frequency = 25khz vg on gate on voltage v in = 12, gcl = 12 10 10.4 10.7 v v in = 12, gcl = 8 7.6 7.9 8.1 v vg off gate off voltage v in = 12v 0.2 0.35 v ig so max gate source current v in = 12v 0.3 a ig sk max gate sink current v in = 12v 0.3 a v inuvlo gate drive undervoltage lockout (note 5) v gcl = 6.5v 7.3 7.5 v current sense t ibl switch current limit blanking time 100 ns v sense sense voltage shutdown voltage v c pulled low l 86 103 120 mv v sensef sense voltage fault threshold 220 300 mv slew control for the following slew tests see test circuit in figure 1b v slewr output voltage slew rising edge r vsl = r csl = 17k 26 v/ m s v slewf output voltage slew falling edge r vsl = r csl = 17k 19 v/ m s vi slewr output current slew rising edge (cs pin v) r vsl = r csl = 17k 2.1 v/ m s vi slewf output current slew falling edge (cs pin v) r vsl = r csl = 17k 2.1 v/ m s supply and protection v inmin minimum input voltage (note 4) v gcl = v in l 2.55 3.6 v i vin supply current (note 3) r vsl = r csl = 17k v in = 12 l 12 40 ma r vsl = r csl = 17k v in = 20 35 55 ma v shdn shutdown turn-on threshold l 1.31 1.39 1.48 v d v shdn shutdown turn-on voltage hysteresis l 50 110 180 mv i shdn shutdown input current hysteresis l 10 24 35 m a v5 5v reference voltage 6.5v v in 20v, iv5 = 5ma 4.85 5 5.20 v 6.5v v in 20v, iv5 = C 5ma 4.80 5 5.15 v iv5 sc 5v reference short-circuit current v in = 6.5v source 10 ma v in = 6.5v sink C10 ma design, characterization and correlation with statistical process controls.the lt1738i is guaranteed and tested to meet performance specifications from C 40 c to 125 c. note 4: output gate drive is enabled at this voltage. the gcl voltage will also determine driver activity. note 5: gate drive is ensured to be on when v in is greater than max value.
4 lt1738 1738fa typical perfor a ce characteristics uw feedback voltage and input current vs temperature negative feedback voltage and input current vs temperature feedback overvoltage shutdown vs temperature error amp transconductance vs temperature error amp output current vs feedback pin voltage from nominal v c pin threshold and clamp voltage vs temperature cs pin trip voltage and cs fault voltage vs temperature shdn pin on and off thresholds vs temperature temperature ( c) 50 25 0 25 50 75 100 125 150 feedback voltage (v) 1738 g01 1.260 1.258 1.256 1.254 1.252 1.250 1.248 1.246 1.244 1.242 1.240 fb input current (na) 750 700 650 600 550 500 450 400 350 300 250 temperature ( c) 50 25 0 25 50 75 100 125 150 negative feedback voltage (v) 1738 g02 2.480 2.485 2.490 2.495 2.500 2.505 2.510 2.515 2.520 nfb input current ( a) 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 temperature ( c) 50 25 0 25 50 75 100 125 150 feedback voltage (v) 1738 g03 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.20 temperature ( c) 50 25 0 25 50 75 100 125 150 transconductance ( mho) 1738 g04 2000 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 feedback pin voltage from nominal (mv) 400 300 200 100 0 100 200 300 400 current ( a) 1738 g05 500 400 300 200 100 0 100 200 300 400 500 ?0 c 125 c 25 c temperature ( c) 50 25 0 25 50 75 100 125 150 v c pin voltage (v) 1738 g06 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 clamp threshold temperature ( c) 50 25 0 25 50 75 100 125 150 cs pin voltage (mv) 1738 g07 240 220 200 180 160 140 120 100 80 fault trip temperature ( c) 50 25 0 25 50 75 100 125 150 shdn pin voltage (v) 1738 g08 1.50 1.45 1.40 1.35 1.30 1.25 on off
5 lt1738 1738fa shdn pin hysteresis current vs temperature v in current vs temperature cs pin to v c pin transfer function slope compensation gate drive high voltage vs temperature gate drive low voltage vs temperature gate drive undervoltage lockout voltage vs temperature v5 voltage vs load current typical perfor a ce characteristics uw temperature ( c) 50 25 0 25 50 75 100 125 150 shdn pin current ( a) 1738 g09 27 25 23 21 19 17 15 cs pin voltage (mv) 0 20 40 60 80 100 120 v c pin voltage (v) 1738 g11 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 t a = 25 c duty cycle (%) 0 20 40 60 80 100 percent of max cs voltage 1738 g12 110 100 90 80 70 60 50 v c pin = 0.9v t a = 25 c temperature ( c) 50 25 0 25 50 75 100 125 150 gate drive a/b pin voltage (v) 1738 g13 10.7 10.6 10.5 10.4 10.3 10.2 10.1 10.0 9.90 9.80 9.70 6.5 6.4 6.3 6.2 6.1 6.0 5.9 5.8 5.7 5.6 5.5 gcl = 12v gcl = 6v v in = 12v no load temperature ( c) 50 25 0 25 50 75 100 125 150 gate drive a/b pin voltage (v) 1738 g14 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 v in = 12v no load temperature ( c) 50 25 0 25 50 75 100 125 150 v in pin voltage (v) 1738 g15 7.3 7.2 7.1 7.0 6.9 6.8 6.7 6.6 6.5 6.4 6.3 gcl = 6v temperature ( c) 50 25 0 25 50 75 100 125 150 ss pin current ( a) 1738 g16 9.5 9.3 9.1 8.9 8.7 8.5 8.3 8.1 7.9 7.7 7.5 ss voltage = 0.9v load current (ma) ?5 ?0 ? 0 51015 v5 pin voltage (v) 1738 g17 5.08 5.06 5.04 5.02 5.00 4.98 4.96 t = 125 c t = 25 c t = 40 c soft-start current vs temperature temperature ( c) 50 ?5 25 75 125 v in current (ma) 150 1738 g10 0 50 100 18 17 16 15 14 13 12 11 10 v in = 12 r vsl , r csl = 4.85k v in = 20 r vsl , r csl = 17k v in = 12 r vsl , r csl = 17k using load of figure 1a f osc = 120khz
6 lt1738 1738fa pi fu ctio s uuu part supply v5 (pin 5): this pin provides a 5v output that can sink or source 10ma for use by external components. v5 source current comes from v in . sink current goes to gnd. v in must be greater than 6.5v in order for this voltage to be in regulation. if this pin is used, a small capacitor (<1 m f) may be placed on this pin to reduce noise. this pin can be left open if not used. gnd (pin 11): signal ground. the internal error amplifier, negative feedback amplifier, oscillator, slew control cir- cuitry, v5 regulator, current sense and the bandgap refer- ence are referred to this ground. keep the connection to this pin, the feedback divider and v c compensation net- work free of large ground currents. shdn (pin 14): the shutdown pin can disable the switcher. grounding this pin will disable all internal circuitry. increasing shdn voltage will initially turn on the internal bandgap regulator. this provides a precision threshold for the turn on of the rest of the ic. as shdn increases past 1.39v the internal ldo regulator turns on, enabling the control and logic circuitry. 24 m a of current is sourced out of the pin above the turn on threshold. this can be used to provide hysteresis for the shutdown function. the hysteresis voltage will be set by the thevenin resistance of the resistor divider driving this pin times the current sourced out. above approximately 2.1v the hysteresis current is removed. there is approxi- mately 0.1v of voltage hysteresis on this pin as well. the pin can be tied high (to v in for instance). v in (pin 17): input supply. all supply current for the part comes from this pin including gate drive and v5 regulator. charge current for gate drive can produce current pulses of hundreds of milliamperes. bypass this pin with a low esr capacitor. when v in is below 2.55v the part will go into supply undervoltage lockout where the gate driver is driven low. this, along with gate drive undervoltage lockout, prevents unpredictable behavior during power up. pgnd (pin 20): power driver ground. this ground comes from the mosfet gate driver. this pin can have several hundred milliamperes of current on it when the external mosfet is being turned off. oscillator sync (pin 6): the sync pin can be used to synchronize the part to an external clock. the oscillator frequency should be set close to the external clock frequency. synchronizing the clock to an external reference is useful for creating more stable positioning of the switcher volt- age and current harmonics. this pin can be left open or tied to ground if not used. c t (pin 7): the oscillator capacitor pin is used in conjunc- tion with r t to set the oscillator frequency. for r t = 16.9k: c osc (nf) = 129/f osc (khz) r t (pin 8): a resistor to ground sets the charge and discharge currents of the oscillator capacitor. the nomi- nal value is 16.9k. it is possible to adjust this resistance 25% to set oscillator frequency more accurately. gate drive gate (pin 1): this pin connects to the gate of an external n-channel mosfet. this driver is capable of sinking and sourcing at least 300ma. the gcl pin sets the upper voltage of the gate drive. the gate pin will not be activated until v in reaches a minimum voltage as defined by the gcl pin (gate undervoltage lockout). the gate drive output has current limit protection to safe guard against accidental shorts. gcl (pin 3): this pin sets the maximum gate voltage to the gate pin to the mosfet gate drive. this pin should be either tied to a zener, a voltage source, or v in . if the pin is tied to a zener or a voltage source, the maximum gate drive voltage will be approximately v gcl C 0.2v. if it is tied to v in , the maximum gate voltage is approximately v in C 1.6.
7 lt1738 1738fa approximately 50 m a of current can be sourced from this pin if v gcl < v in C 0.8v. this pin also controls undervoltage lockout of the gate drive. if the pin is tied to a zener or voltage source, the gate drive will not be enabled until v in > v gcl + 0.8v. if this pin is tied to v in , then undervoltage lockout is disabled. there is an internal 19v zener tied from this pin to ground to provide a fail-safe for maximum gate voltage. slew control cap (pin 2): this pin is the feedback node for the external voltage slewing capacitor. normally a small 1pf to 5pf capacitor is connected from this pin to the drain of the mosfet. the voltage slew rate is inversely proportional to this capacitance and proportional to the current that the part will sink and source on this pin. that current is inversely proportional to r vsl . r csl (pin 15): a resistor to ground sets the current slew rate for the external drive mosfet during switching. the minimum resistor value is 3.3k and the maximum value is 68k. the time to slew between on and off states of the mosfet current will determine how the di/dt related harmonics are reduced. this time is proportional to r csl and r s (the current sense resistor) and maximum current. longer times produce a greater reduction of higher fre- quency harmonics. r vsl (pin 16): a resistor to ground sets the voltage slew rate for the drain of the external drive mosfet. the minimum resistor value is 3.3k and the maximum value is 68k. the time to slew between on and off states on the mosfet drain voltage will determine how dv/dt related harmonics are reduced. this time is proportional to r vsl , c v and the input voltage. longer times produce more rolloff of harmonics. c v is the equivalent capacitance from cap to the drain of the mosfet. switch mode control ss (pin 3): the ss pin allows for ramping of the switch current threshold at startup. normally a capacitor is placed on this pin to ground. an internal 9 m a current source will charge this capacitor up. the voltage on the v c pin cannot exceed the voltage on ss. thus peak current will ramp up as the ss pin ramps up. during a short circuit fault the ss pin will be discharged to ground thus reinitializing soft- start. when ss is below the v c clamp voltage the v c pin will closely track the ss pin. this pin can be left open if not used. cs (pin 4): this is the input to the current sense amplifier. it is used for both current mode control and current slewing of the external mosfet. current sense is accom- plished via a sense resistor (r s ) connected from the source of the external mosfet to ground. cs is connected to the top of r s . current sense is referenced to the gnd pin. the switch maximum operating current will be equal to 0.1v/r s . at cs = 0.1v, the gate driver will be immediately turned off (no slew control). if cs = 0.22v in addition to the drivers being turned off, v c and ss will be discharged to ground (short-circuit protec- tion). this will hasten turn off on subsequent cycles. fb (pin 9): the feedback pin is used for positive voltage sensing. it is the inverting input to the error amplifier. the noninverting input of this amplifier connects internally to a 1.25v reference. if the voltage on this pin exceeds the reference by 220mv, then the output driver will immediately turn off the external mosfet (no slew control). this provides for output over- voltage protection when this input is below 0.9v then the current sense blanking will be disabled. this will assist start up. nfb (pin 10): the negative feedback pin is used for sensing a negative output voltage. the pin is connected to the inverting input of the negative feedback amplifier through a 100k source resistor. the negative feedback amplifier provides a gain of C0.5 to the fb pin. the nominal regulation point would be C2.5v on nfb. this pin should be left open if not used. if nfb is being used then overvoltage protection will occur at 0.44v below the nfb regulation point. at nfb < C1.8 current sense blanking will be disabled. pi fu ctio s uuu
8 lt1738 1738fa v c (pin 12): the compensation pin is used for frequency compensation and current limiting. it is the output of the error amplifier and the input of the current comparator. loop frequency compensation can be performed with an rc network connected from the v c pin to ground. the voltage on v c is proportional to the switch peak current. the normal range of voltage on this pin is 0.25v to 1.27v. however, during slope compensation the upper clamp voltage is allowed to increase with the compensation. during a short-circuit fault the v c pin will be discharged to ground. pi fu ctio s uuu block diagra w figure 1a. typical test circuitry + v c nfb fb 1738 bd ss slew control v reg v in v5 to drivers sq ff r oscillator + negative feedback amp + + error amp 1.25v 100k 50k comp + sense amp shdn r vsl r csl regulator r t c t cap gate gcl pgnd sync gnd sub cs 4 11 6 7 8 13 9 10 14 17 5 15 16 12 20 1 2 3 figure 1b. test circuit for slew + 5pf in5819 20ma 2 1738 f01a zvn3306a 10 gate cap + 5pf in5819 0.9a 0.1 1738 f01b si4450dy 10 gate cs cap test circuits
9 lt1738 1738fa operatio u in noise sensitive applications switching regulators tend to be ruled out as a power supply option due to their propensity for generating unwanted noise. when switch- ing supplies are required due to efficiency or input/output constraints, great pains must be taken to work around the noise generated by a typical supply. these steps may include pre and post regulator filtering, precise synchro- nization of the power supply oscillator to an external clock, synchronizing the rest of the circuit to the power supply oscillator or halting power supply switching during noise sensitive operations. the lt1738 greatly simplifies the task of eliminating supply noise by enabling the design of an inherently low noise switching regulator power supply. the lt1738 is a fixed frequency, current mode switching regulator with unique circuitry to control the voltage and current slew rates of the output switch. current mode control provides excellent ac and dc line regulation and simplifies loop compensation. slew control capability provides much greater control over the power supply components that can create con- ducted and radiated electromagnetic interference. com- pliance with emi standards will be an easier task and will require fewer external filtering components. the lt1738 uses an external n-channel mosfet as the power switch. this allows the user to tailor the drive conditions to a wide range of voltages and currents. current mode control referring to the block diagram. a switching cycle begins with an oscillator discharge pulse, which resets the rs flip-flop, turning on the gate driver and the external mosfet. the switch current is sensed across the external sense resistor and the resulting voltage is amplified and compared to the output of the error amplifier (v c pin). the driver is turned off once the output of the current sense amplifier exceeds the voltage on the v c pin. in this way pulse by pulse current limit is achieved. internal slope compensation is provided to ensure stabil- ity under high duty cycle conditions. output regulation is obtained using the error amp to set the switch current trip point. the error amp is a transconductance amplifier that integrates the difference between the feedback output voltage and an internal 1.25v reference. the output of the error amp adjusts the switch current trip point to provide the required load current at the desired regulated output voltage. this method of controlling current rather than voltage pro- vides faster input transient response, cycle-by-cycle current limiting for better output switch protection and greater ease in compensating the feedback loop. the v c pin is used for loop compensation and current limit adjustment. during normal operation the v c voltage will be between 0.25v and 1.27v. an external clamp on v c or ss may be used for lowering the current limit. the negative voltage feedback amplifier allows for direct regulation of negative output voltages. the voltage on the nfb pin gets amplified by a gain of C 0.5 and driven on to the fb input, i.e., the nfb pin regulates to C2.5v while the amplifier output internally drives the fb pin to 1.25v as in normal operation. the negative feedback amplifier input impedance is 100k (typ) referred to ground. soft-start control of the switch current during start up can be obtained by using the ss pin. an external capacitor from ss to ground is charged by an internal 9 m a current source. the voltage on v c cannot exceed the voltage on ss. thus as the ss pin ramps up the v c voltage will be allowed to ramp up. this will then provide for a smooth increase in switch maximum current. ss will be discharged as a result of the cs voltage exceeding the short circuit threshold of approximately 0.22v. slew control control of output voltage and current slew rates is achieved via two feedback loops. one loop controls the mosfet drain dv/dt and the other loop controls the mosfet di/dt. the voltage slew rate uses an external capacitor between cap and the mosfet drain. this integrating cap closes the voltage feedback loop. the external resistor r vsl sets the current for the integrator. the voltage slew rate is thus inversely proportional to both the value of capacitor and r vsl .
10 lt1738 1738fa the current slew feedback loop consists of the voltage across the external sense resistor, which is internally amplified and differentiated. the derivative is limited to a value set by r csl . the current slew rate is thus inversely proportional to both the value of sense resistor and r csl. the two control loops are combined internally so that a smooth transition from current slew control to voltage slew control is obtained. when turning on, the driver current will slew before voltage. when turning off, voltage will slew before current. in general it is desirable to have r vsl and r csl of similar value. internal regulator most of the control circuitry operates from an internal 2.4v low dropout regulator that is powered from v in . the internal low dropout design allows v in to vary from 2.7v to 20v with stable operation of the controller. when shdn < 1.3v the internal regulator is completely disabled. 5v regulator a 5v regulator is provided for powering external circuitry. this regulator draws current from v in and requires v in to be greater than 6.5v to be in regulation. it can sink or source 10ma. the output is current limited to prevent against destruction from accidental short circuits. safety and protection features there are several safety and protection features on the chip. the first is overcurrent limit. normally the gate driver will go low when the output of the internal sense amplifier exceeds the voltage on the v c pin. the v c pin is clamped such that maximum output current is attained when the cs pin voltage is 0.1v. at that level the outputs will be immediately turned off (no slew). the effect of this control is that the output voltage will foldback with overcurrent. in addition, if the cs voltage exceeds 0.22v, the v c and ss pins will be discharged to ground, resetting the soft-start function. thus if a short is present this will allow for faster mosfet turnoff and less mosfet stress. if the voltage on the fb pin exceeds regulation by approxi- mately 0.22v, the outputs will immediately go low. the implication is that there is an overvoltage fault. the voltage on gcl determines two features. the first is the maximum gate drive voltage. this will protect the mosfet gate from overvoltage. with gcl tied to a zener or an external voltage source then the maximum gate driver voltage is approximately v gcl C 0.2v. if gcl is tied to v in , then the maximum gate voltage is determined by v in and is approximately v in C 1.6v. there is an internal 19v zener on the gcl pin that prevents the gate driver pin from exceeding approxi- mately 19v. in addition, the gcl voltage determines undervoltage lockout of the gate drive. this feature disables the gate driver if v in is too low to provide adequate voltage to turn on the mosfet. this is helpful during start up to insure the mosfet has sufficient gate drive to saturate. if gcl is tied to a voltage source or zener less than 6.8v, the gate driver will not turn on until v in exceeds gcl voltage by 0.8v. for v gcl above 6.5v, the gate drive is insured to be off for v in < 7.3v and it will be turned on by v gcl + 0.8v. if gcl is tied to v in , the gate driver is always on (undervoltage lockout is disabled). the gate drive has current limits for the drive currents. if the sink or source current is greater than 300ma then the current will be limited. the v5 regulator also has internal current limiting that will only guarantee 10ma output current. there is also an on chip thermal shutdown circuit that will turn off the output in the event the chip temperature rises to dangerous levels. thermal shutdown has hysteresis that will cause a low frequency (<1khz) oscillation to occur as the chip heats up and cools down. the chip has an undervoltage lockout feature that will force the gate driver low in the event that v in drops below 2.5v. this insures predictable behavior during start up and shut down. shdn can be used in conjuction with an external resistor divider to completely disable the part if the input voltage is too low. this can be used to insure adequate voltage to reliably run the converter. see the section in applications information. table 1 summarizes these features. operatio u
11 lt1738 1738fa applicatio s i for atio wu u u operatio u reducing emi from switching power supplies has tradi- tionally invoked fear in designers. many switchers are designed solely on efficiency and as such produce wave- forms filled with high frequency harmonics that then propagate through the rest of the system. the lt1738 provides control over two of the more impor- tant variables for controlling emi with switching inductive loads: switch voltage slew rate and switch current slew rate. the use of this part will reduce noise and emi over conventional switch mode controllers. because these variables are under control, a supply built with this part will exhibit far less tendency to create emi and less chance of encountering problems during production. it is beyond the scope of this data sheet to get into emi fundamentals. application note 70 contains much infor- mation concerning noise in switching regulators and should be consulted. oscillator frequency the oscillator determines the switching frequency and therefore the fundamental positioning of all harmonics. the use of good quality external components is important to ensure oscillator frequency stability. the oscillator is of a sawtooth design. a current defined by external resistor r t is used to charge and discharge the capacitor c t . the discharge rate is approximately ten times the charge rate. by allowing the user to have control over both compo- nents, trimming of oscillator frequency can be more easily achieved. the external capacitance c t is chosen by: cnf f khz r k t t () ()() = w 2180 where f is the desired oscillator frequency in khz. for r t equal to 16.9k, this simplifies to: cnf f khz t () () = 129 e.g., c t = 1.29nf for f = 100khz nominally r t should be 16.9k. since it sets up current, its temperature coefficient should be selected to compliment the capacitor. ideally, both should have low temperature coefficients. table 1. safety and protection features feature function effect on gate driver slew control effect on v c , ss maximum current fault turn off fet at maximum immediately goes low overridden none switch current (v sense = 0.1) short-circuit fault turn off fet and reset v c immediately goes low overridden discharge v c , ss for short-circuit (v sense = 0.22) to gnd overvoltage fault turn off driver if fb > v reg + 0.22v immediately goes low overridden none (output overvoltage) gcl clamp set max gate voltage to prevent limits max voltage none none fet gate breakdown gate drive disable gate drive when v in immediately goes low overridden none undervoltage lockout is too low. set via gcl pin thermal shutdown turn off driver if chip immediately goes low overridden none temperature is too hot v in undervoltage lockout disable part when v in @ 2.55v immediately goes low overridden none gate drive source and sink current limit limit gate drive current limit drive current none none v5 source/sink current limit limit current from v5 none none none shutdown disable part when shdn <1.3v
12 lt1738 1738fa applicatio s i for atio wu u u oscillator frequency is important for noise reduction in two ways. first the lower the oscillator frequency the lower the waveforms harmonics, making it easier to filter them. second the oscillator will control the placement of the output voltage harmonics which can aid in specific prob- lems where you might be trying to avoid a certain fre- quency bandwidth. oscillator sync if a more precise frequency is desired (e.g., to accurately place harmonics) the oscillator can be synchronized to an external clock. set the rc timing components for an oscillator frequency 10% lower than the desired sync frequency. drive the sync pin with a square wave (with greater than 2v amplitude). the rising edge of the sync square wave will initiate clock discharge. the sync pulse should have a minimum pulse width of 0.5 m s. be careful in syncing to frequencies much different from the part since the internal oscillator charge slope deter- mines slope compensation. it would be possible to get into subharmonic oscillation if the sync doesnt allow for the charge cycle of the capacitor to initiate slope compensa- tion. in general, this will not be a problem until the sync frequency is greater than 1.5 times the oscillator free-run frequency. slew rate setting the primary reason to use this part is to gain advantage of lower emi and noise due to the slew control. the rolloff in higher frequency harmonics has its theoretical basis with two primary components. first, the clock frequency sets the fundamental positioning of harmonics and second, the associated normal frequency rolloff of harmonics. this part creates a second higher frequency rolloff of harmonics that inversely depends on the slew time, the time that voltage or current spends between the off state and on state. this time is adjustable through the choice of the slew resistors, the external resistors to ground on the r vsl and r csl pins and the external components used for the external voltage feedback capacitor c v (from cap to the mosfet drain) and the sense resistor. lower slew rates (longer slew times, lower rolloff frequency for har- monics ) are created with higher values of r vsl , r csl , c v and the current sense resistor. setting the voltage and current slew rates should be done empirically. the most practical way of determining these components is to set c v and the sense resistor value. then, start by making r vsl , r csl each a 50k resistor pot in series with 3.3k. starting from the lowest resistor setting (fast slew) adjust the pots until the noise level meets your guidelines. note that slower slewing wave- forms will dissipate more power so that efficiency will drop. you can monitor this as you make your slew adjust- ment by measuring input and output voltage and their respective currents. monitor the mosfet temperature as slew rates are slowed. the mosfet will heat up as efficiency decreases. measuring noise should be done carefully. it is easy to introduce noise by poor measurement techniques. con- sult an70 for recommended measurement techniques. keeping probe ground leads very short is essential. usually it will be desirable to keep the voltage and current slew resistors approximately the same. there are circum- stances where a better optimization can be found by adjusting each separately, but as these values are sepa- rated further, a loss of independence of control may occur. it is possible to use a single slew setting resistor. in this case the r vsl and r csl pins are tied together. a resistor with a value of 1.8k to 34k (one half the individual resis- tors) can then be tied from these pins to ground. in general only the r csl value will be available for adjust- ment of current slew. the current slew time also depends on the current sense resistor but this resistor is normally set with consideration of the maximum current in the mosfet. setting the voltage slew also involves selection of the capacitor c v . the voltage slew time is proportional to the output voltage swing (basically input voltage), the external voltage feedback capacitor and the r vsl value. thus at higher input voltages smaller capacitors will be used with lower r vsl values. for a starting point use table 2.
13 lt1738 1738fa positive output voltage setting sensing of a positive output voltage is usually done using a resistor divider from the output to the fb pin. the positive input to the error amp is connected internally to a 1.25v bandgap reference. the fb pin will regulate to this voltage. referring to figure 3, r1 is determined by: rr v out 12 125 1 =- ? ? ? ? . the fb bias current represents a small error and can usually be ignored for values of r1||r2 up to 10k. one word of caution, sometimes a feedback zero is added to the control loop by placing a capacitor across r1. if the feedback capacitively pulls the fb pin above the internal regulator voltage (2.4v), output regulation may be dis- rupted. a series resistance with the feedback pin can eliminate this potential problem. there is an internal clamp on fb that clamps at 0.7v above the regulation voltage that should also help prevent this problem. applicatio s i for atio wu u u smaller value capacitors can be made in two ways. the first is simply combining two capacitors in series. the equivalent capacitance is then (c1 ? c2)/(c1 + c2). the second method makes use of a capacitor divider. care should be taken that the voltage rating of the capacitor satisfies the full voltage swing thus essentially the same rating as the mosfet. the equivalent slew capacitance for figure 2 is (c1 ? c2)/(c1 + c2 + c3). negative output voltage setting negative output voltage can be sensed using the nfb pin. in this case regulation will occur when the nfb pin is at C2.5v. the nominal input bias current for the nfb is C25 m a (i nfb ), which needs to be accounted for in setting up the divider. referring to figure 4, r1 is chosen such that: rr v ra out 12 25 25 2 25 = - +m ? ? ? ? . . a suggested value for r2 is 2.5k. the nfb pin is normally left open if the fb pin is being used. c1 mosfet drain c2 cap c3 1738 f02 table 2 input voltage capacitor value < 25v 5pf 50v 2.5pf 100v 1pf figure 2 figure 3 figure 4 fb pin 1738 f03 v out r2 r1 nfb pin i nfb 1738 f04 ? out r2 r1 dual polarity output voltage sensing certain applications may benefit from sensing both posi- tive and negative output voltages. when doing this each output voltage resistor divider is individually set as previ- ously described. when both fb and nfb pins are used, the lt1738 will act to prevent either output from going beyond its set output voltage. the highest output (lightest load) will dominate control of the regulator. this technique would prevent either output from going unregulated high at no load. however, this technique will also compromise output load regulation. shutdown if shdn is pulled low, the regulator will turn off. as the shdn pin voltage is increased from ground the internal bandgap regulator will be powered on. this will set a 1.39v threshold for turn on of the internal regulator that runs
14 lt1738 1738fa applicatio s i for atio wu u u most of the control circuitry of the regulator. note after the control circuitry powers on, gate driver activity will depend on the voltage of v in with respect to the voltage on gcl. as the shdn pin enables the internal regulator a 24 m a current will be sourced from the pin that can provide hysteresis for undervoltage lockout. this hysteresis can be used to prevent part shutdown due to input voltage sag from an initial high current draw. in addition to the current hysteresis, there is also approxi- mately 100mv of voltage hysteresis on the shdn pin. when the shdn pin is greater than 2.2v, the hysteretic current from the part will be reduced to essentially zero. if a resistor divider is used to set the turn on threshold then the resistors are determined by the following equations: v ra rb rb v vra v ra rb i on shdn hyst shdn shdn = + ? ? ? ? = d + ? ? ? ? ra rb v in shdn reworking these equations yields: ra vv vv iv rb vv vv ivv hyst shdn on shdn shdn shdn hyst shdn on shdn shdn on shdn = -d () () = -d () - () [] so if we wanted to turn on at 20v with 2v of hysteresis: ra vvvv av k rb vvvv av v k = - m = = - m- () = 2 1 39 20 0 1 24 1 39 23 4 2 1 39 20 0 1 24 20 1 39 175 . . . . . . . . resistor values could be altered further by adding zeners in the divider string. a resistor in series with shdn pin could further change hysteresis without changing turn on voltage. frequency compensation loop frequency compensation is accomplished by way of a series rc network on the output of the error amplifier (v c pin). v c pin 1738 f05 r vc 2k c vc 0.01 f c vc2 4.7nf figure 5 referring to figure 5, the main pole is formed by capacitor c vc and the output impedance of the error amplifier (approximately 400k w ). the series resistor r vc creates a zero which improves loop stability and transient re- sponse. a second capacitor c vc2 , typically one-tenth the size of the main compensation capacitor, is sometimes used to reduce the switching frequency ripple on the v c pin. v c pin ripple is caused by output voltage ripple attenuated by the output divider and multiplied by the error amplifier. without the second capacitor, v c pin ripple is: v vgmr v cpinripple ripple vc out = 125 . where v ripple = output ripple (v p-p ) gm = error amplifier transconductance r vc = series resistor on v c pin v out = dc output voltage to prevent irregular switching, v c pin ripple should be kept below 50mv p-p . worst-case v c pin ripple occurs at maximum output load current and will also be increased if poor quality (high esr) output capacitors are used. the addition of a 0.0047 m f capacitor for c vc2 pin reduces switching frequency ripple to only a few millivolts. a low value for r vc will also reduce v c pin ripple, but loop phase margin may be inadequate.
15 lt1738 1738fa applicatio s i for atio wu u u setting current limit the sense resistor sets the value for maximum operating current. when the cs pin voltage is 0.1v the gate driver will immediately go low (no slew control). therefore the sense resistor value should be set to r s = 0.1v/i sw(peak) , where i sw(peak) is the peak current in the mosfet. i sw(peak) will depend on the topology and component values and tolerances. certainly it should be set below the saturation current value for the inductor. if the cs pin voltage is 0.22v in addition to the driver going low, v c and ss will be discharged to ground. this is to provide additional protection in the event of a short circuit. by discharging v c and ss the mosfet will not be stressed as hard on subsequent cycles since the current trip will be set lower. turn off of the mosfet will normally be inhibited for about 100ns at the start of every turn on cycle. this is to prevent noise from interfering with normal operation of the control- ler. this current sense blanking does not prevent the out- puts from being turned off in the event of a fault. slewing of the gate voltage effectively provides additional blanking. traces to the sense resistor should be kept short and wide to minimize resistance and inductance. large interwinding capacitance in the transformer or high capacitance on the drain of the mosfet will produce a current pulse through the sense resistor during drain voltage slewing. the mag- nitude of the pulse is c ? dv/dt where c is the capacitance and dv/dt is the voltage slew rate which is controlled by the part. this pulse will increase the sensed current on switch turn on and if large enough can cause premature mosfet turn off. if this occurs, the inductor transformer may need a different winding technique (see an39) or alternatively, a blanking circuit can be used. please contact the ltc ap- plications group for support if required. soft-start the soft-start pin is used to provide control of switching current during startup. the maximum voltage on the v c pin is approximately the voltage on the ss pin. a current source will linearly charge a capacitor on the ss pin. the v c pin voltage will thus ramp up also. the approximate time for the voltage on these pins to ramp up is (1.31v/9 m a) ? c ss or approximately 146ms per m f. the soft-start current will be initiated as soon as the part turns on. soft-start will be reinititated after a short-circuit fault. thermal considerations most of the ic power dissipation is derived from the v in pin. the v in current depends on a number of factors including: oscillator frequency; loads on v5; slew settings; gate charge current. additional power is dissipated if v5 sinks current and during the mosfet gate discharge. the power dissipation in the ic will be the sum of: 1) the rms v in current times v in 2) v5 rms sink current times 5v 3) the gate drives rms discharge current times voltage. because of the strong v in component it is advantageous to operate the lt1738 at as low a v in as possible. it is always recommended that package temperature be measured in each application. the part has an internal thermal shutdown to minimize the chance of ic destruc- tion but this should not replace careful thermal design. the thermal shutdown feature does not protect the exter- nal mosfet. a separate analysis must be done for this device to insure that it is operating within safe limits. once ic power dissipation, p dis , is determined die junc- tion temperature is then computed as: t j = t amb + p dis ? q ja where t amb is ambient temperature and q ja is the package thermal resistance. for the 20-pin ssop, q ja is 100 c/w. choosing the inductor for a boost converter, inductor selection involves trade- offs of size, maximum output power, transient response and filtering characteristics. higher inductor values pro- vide more output power and lower input ripple. however, they are physically larger and can impede transient re- sponse. low inductor values have high magnetizing cur- rent, which can reduce maximum power and increase input current ripple.
16 lt1738 1738fa the following procedure can be used to handle these trade-offs: 1. assume that the average inductor current for a boost converter is equal to load current times v out /v in and decide whether the inductor must withstand continu- ous overload conditions. if average inductor current at maximum load current is 0.5a, for instance, a 0.5a inductor may not survive a continuous 1.5a overload condition. also be aware that boost converters are not short-circuit protected, and under output short condi- tions, only the available current of the input supply limits inductor current. 2. calculate peak inductor current at full load current to ensure that the inductor will not saturate. peak current can be significantly higher than output current, espe- cially with smaller inductors and lighter loads, so dont omit this step. powdered iron cores are forgiving because they saturate softly, whereas ferrite cores satu- rate abruptly. other core materials fall in between. the following formula assumes continuous mode opera- tion but it errs only slightly on the high side for discon- tinuous mode, so it can be used for all conditions. ii v v vv v lfv peak out out in in out in out =+ () ? ? ? ? 2 l = inductance value v in = supply voltage v out = output voltage i = output current f = oscillator frequency 3. choose a core geometry. for low emi problems a closed structure should be used such as a pot core, er core or toroid (see an70 appendix i). 4. select an inductor that can handle peak current, average current (heating effects) and fault current. 5. finally, double check output voltage ripple. the experts in the linear technology applications depart- ment have experience with a wide range of inductor types and can assist you in making a good choice. capacitors correct choice of input and output capacitors can be very important to low noise switcher performance. noise de- pends more on the esr of the capacitors. in addition lower esr can also improve efficiency. input capacitors must also withstand surges that occur during the switching of some types of loads. some solid tantalum capacitors can fail under these surge conditions. design note 95 offers more information but the following is a brief summary of capacitor types and attributes. aluminum electrolytic: low cost and higher voltage. they will typically only be used for higher voltage applications. large values will be needed for low esr. specialty polymer aluminum: panasonic has come out with their series cd capacitors. while they are only avail- able for voltages below 16v, they have very low esr and good surge capability. solid tantalum: small size and low impedance. typically the maximum voltage rating is 50v. with large surge currents the capacitor may need to be derated or you need a special type such as the avx tps line. os-con: lower impedance than aluminum but only avail- able for 35v or less. form factor may be a problem. ceramic: generally used for high frequency and high voltage bypass. they may resonate with their esl before esr becomes dominant. recent multilayer ceramic (mlc) capacitors provide larger capacitance with low esr. there are continuous improvements being made in ca- pacitors so consult with manufacturers as to your specific needs. input capacitors the input capacitor should have low esr at high frequen- cies since this will be an important factor concerning how much conducted noise is generated. there are two separate requirements for input capacitors. the first is for the supply to the parts v in pin. the v in pin will provide current for the part itself and the gate charge current. applicatio s i for atio wu u u
17 lt1738 1738fa the worst component from an ac point is the gate charge current. the actual peak current depends on gate capaci- tance and slew rate, being higher for larger values of each. the total current can be estimated by gate charge and frequency of operation. because of the slewing with this part gate charge is spread out over a longer time period than with a normal fet driver. this reduces capacitance requirements. typically the current will have spikes of under 100ma located at the gate voltage transitions. this is charge/ discharge to and from the threshold voltage. most slewing occurs with the gate voltage near threshold. since the parts v in will typically be under 15v many options are available for choice of capacitor. values of input capacitor for just the v in requirement will typically be in the 50 m f range with an esr of under 0.1 w . in addition to the parts supply, decoupling of the supply to the inductor needs to be considered. if this is the same supply as the v in pin then that capacitor will need to be increased. however, often with this part the inductor supply will be a higher voltage and as such will use a separate capacitor. the inductors decoupling capacitor will see the switch current as ripple. the above switch current computation can be used to estimate the capacity for these capacitors. c v i esr dc f in cap sw max min = d d - 1 () where d v cap is the allowed sag on the input capacitor. esr is the equivalent series resistance for the cap. in general allowed sag will be a few tenths of a volt. output filter capacitor the output capacitor is chosen both for capacity and esr. the capacity must supply the load current in the switch on state. while slew control reduces higher frequency com- ponents of the ripple current in the capacitor, the capacitor esr and the magnitude of the output ripple current controls the fundamental component. esr should also be low to reduce capacitor dissipation. typically esr should be below 0.05 w . the capacitance value can be computed by consideration of desired load ripple, duty cycle and esr. c v i esr dc f out out lmax min = d d - 1 () mosfet selection there is a wide variety of mosfets to choose from for this part. the part will work with either normal threshold (3v to 4v) or logic level threshold devices (1v to 2v). select a voltage rating to insure under worst-case condi- tions that the mosfet will not break down. next choose an r on sufficiently low to meet both the power dissipation capabilities of the mosfet package as well as overall efficiency needs of the converter. the lt1738 can handle a large range of gate charges. however at very large charge stability may be affected. the power dissipation in the mosfet depends on several factors. the primary element is i 2 r heating when the device is on. in addition, power is dissipated when the device is slewing. an estimate for power dissipation is: pv i i i vr i i v i fi r dc in sr in on sr on = + d + -+ d ? ? ? ? ? ? ? ? ? ? ? y ? ? t ? ? + 2 2 22 2 2 2 4 3 4 where i is the average current, d i is the ripple current in the switch, i sr is the current slew rate, v sr is the voltage slew rate, f is the oscillator frequency, dc is the duty cycle and r on is the mosfet on-resistance. setting gcl voltage setting the voltage on the gcl pin depends on what type of mosfet is used and the desired gate drive undervolt- age lockout voltage. applicatio s i for atio wu u u
18 lt1738 1738fa applicatio s i for atio wu u u first determine the maximum gate drive that you require. typically you will want it to be at least 2v greater than the rated threshold. higher voltages will lower the on resis- tance and increase efficiency. be certain to check the maximum allowed gate voltage. often this is 20v but for some logic threshold mosfets it is only 8v to 10v. v gcl needs to be set approximately 0.2v above the desired max gate threshold. in addition v in needs to be at least 1.6v above the gate voltage. the gcl pin can be tied to v in which will result in a maximum gate voltage of v in C 1.6v. this pin also controls undervoltage lockout of the gate drive. the undervoltage lockout will prevent the mosfet from switching until there is sufficient drive present. if gcl is tied to a voltage source or zener less than 6.8v, the gate drivers will not turn on until v in exceeds the gcl voltage by 0.8v. for v gcl above 6.5v, the gate drive is insured to be off for v in < 7.3v and they will be turned on by v gcl + 0.8v. if gcl is tied to v in , the gate driver is always on (undervoltage lockout is disabled). approximately 50 m a of current can be sourced from this pin if v in > v gcl + 0.8v. this could be used to bias a zener. the gcl pin has an internal 19v zener to ground that will provide a failsafe for maximum gate voltage. as an example say we are using a siliconix si4480dy which has r ds(on) rated at 6v. to get 6v, v gcl needs to be set to 6.2v and v in needs to be at least 7.6v. gate driver considerations in general, the mosfet should be positioned as close to the part as possible to minimize inductance. when the part is active the gate drive will be pulled low to less than 0.2v. when the part is off, the gate drive contains a 40k resistor in series with a diode to ground that will offer passive holdoff protection. if you are using some logic level mosfets this might not be sufficient. a resistor may be placed from gate to ground, however the value should be reasonably high to minimize dc losses and possible ac issues. the gate drive source current comes from v in . the sink current exits through pgnd. in general the decoupling cap should be placed close to these two pins. switching diodes in general, switching diodes should be schottky diodes. size and breakdown voltage depend on the specific con- verter. a lower forward drop will improve converter effi- ciency. no other special requirements are needed. pcb layout considerations as with any switcher, careful consideration should be given to pc board layout. because this part reduces high fre- quency emi, the board layout is less critical. however, high currents and voltages still produce the need for careful board layout to eliminate poor and erratic performance. basic considerations keep the high current loops physically small in area. the main loops are shown in figure 6: the power switch loops (a) and the rectifier loop (b). these loops can be kept small by physically keeping the components close to one an- other. in addition, connection traces should be kept wide to lower resistance and inductances. components should be placed to minimize connecting paths. careful attention to ground connections must also be maintained. be care- ful that currents from different high current loops do not get coupled into the ground paths of other loops. using singular points of connection for the grounds is the best way to do this. the two major points of connection are the bottom of the input decoupling capacitor and the bottom of the output decoupling capacitor. typically, the sense resistor device pgnd and device gnd will tie to the bottom of the input capacitor. c out b a v out v in gate cs 1738 f06 c in figure 6
19 lt1738 1738fa package descriptio u g package 20-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. applicatio s i for atio wu u u there are two other loops to pay attention to. the current slew involves a high bandwidth control that goes through the mosfet switch, the sense resistor and into the cs pin of the part and out the gate pin to the mosfet. trace inductance and resistance should be kept low on the gate drive trace. the cs trace should have low inductance. finally, care should be taken with the cap pin. the part will tolerate stray capacitance to ground on this pin (<5pfs). however, stray capacitance to the mosfet drain should be minimized. this path would provide an alternate ca- pacitive path for the voltage slew. more help an70 contains information about low noise switchers and measurement of noise and should be consulted. an19 and an29 also have general knowledge concerning switching regulators. also, our application department is always ready to lend a helping hand. g20 ssop 0802 0.09 ?0.25 (.0035 ?.010) 0 ?8 0.55 ?0.95 (.022 ?.037) 5.00 ?5.60** (.197 ?.221) 7.40 ?8.20 (.291 ?.323) 1234 5 6 7 8910 6.90 ?7.50* (.272 ?.295 ) 17 18 14 13 12 11 15 16 19 20 2.0 (.079) 0.05 (.002) 0.65 (.0256) bsc 0.22 ?0.38 (.009 ?.015) millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 ?5.7 7.8 ?8.2 recommended solder pad layout 1.25 0.12
20 lt1738 1738fa part number description comments lt1683 ultralow noise push-pull dc/dc controller dual output (push-pull) current mode architecture. lt1425 isolated flyback switching regulator excellent regulation without transformer third winding lt1533 ultralow noise 1a switching regulator push-pull design for low noise isolated supplies lt1534 ultralow noise 2a switching regulator ultralow noise regulator for boost topologies lt1576 1.5a, 200khz step-down switching regulator constant frequency, 1.21v reference voltage lt176x family low dropout, low noise linear regulator 150ma to 3a, sot-23 to to-220 lt1777 low noise step-down switching regulator programmable di/dt; internally limited dv/dt ltc1922-1 synchronous phase modulated full-bridge controller adaptive directsense tm zero voltage switching, 50w to kilowatts, synchronous rectification lt3439 ultralow noise transformer driver 1a push-pull dc/dc transformer driver directsense is a trademark of linear technology corporation. lt/tp 1202 1k rev a ? printed in usa ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com typical applicatio u related parts ultralow noise 30w offline power supply + + + + + 14 5 6 7 8 16 15 9 shdn v5 sync c t r t r vsl r csl f b 2 1 4 18 20 12 cap gate cs nc pgnd v c 13 11 3 u3 lt1738 v in nc nfb ss gnd gcl 12v in755 a 165k 165k 51k 3.9k 3.9k 19.6k 1.8nf 2n2222 2n2222 510k 510k 100k 2w 56 f 35v 5pf 5pf 600v 470pf coll rmio r top comp v + ref 65 3 2 8 4 7 v out 5 4 6 iso1 cny17-3 u2 lt1431 1k 1k 0.1 f 38.3k 1% 10k 1% mtp2n60e note: pin 2 of lt1738 must be laid out away from fast slewing nodes unless otherwise noted: all resistors 1206, 5% br1: general instruments w06g c2, c3, c4: sanyo mv-gx 100 f 400v p6ke200a mur160 d4 ba521 10 0.1 f 250vac ?2 1m 1m 10nf v bias x1 x3 90vac to 264vac +v out 12v 2.5a ? out c4 330 f 25v c3 330 f 25v c2 330 f 25v br1 3 6 5 11 1 7 12 8 a1 a2 1738 ta02 ka t1 1 2 3 g-f g-s 17 19 10 d1 0.068 1/2w 1k 0.22 f l1 danger: high voltage input filter is required to attenuate switching frequency harmonics and pass fcc class b (lt1738 does not attenuate these low f requency harmonics) main advantage with lt1738 is it makes suppressing the high frequency noise and emi easy. this is particularly useful for medic al devices because the ac line to earth gnd caps on the input filter can be eliminated; allowing the device to pass the earth gnd leakage current medical specifications. d1: mbr20200ct l1: hm18-10001 t1: premier magnetics pol-15033 v bias

▲Up To Search▲

Price & Availability of LT1738EGTR

	To Download LT1738EGTR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .